Mdio bus goldschmidt@gmail. The target devices that are being managed by the MDC are referred to as A long-time lurker writes: I'm aware that there are many, many posts on the issue of using two or more Ethernet PHYs with a single PS MAC on a shared MDIO bus. For some reason I am not able to get it properly configured. In the Linux kernel, the following vulnerability has been resolved: net: dsa: mv88e6xxx: Correct check for empty list Since commit a3c53be55c95 ("net: dsa: Anyway it is also possible to talk via MDIO bus directly through the IP registers (as stated on the Datasheet (DS580) at page 16. ethernet-ffffffff: MDIO device at address 1 is missing. From datasheet: As you can see here, output data must change at the latest 20ns Saved searches Use saved searches to filter your results more quickly During the MDIO bus driver initialization, PHYs on this bus are probed using the _ADR object as shown below and are registered on the MDIO bus. MDIO is a management interface between a MAC and one or more PHYs. I Hi @badFITimageto@8,. Values greater than IEEE 802. We are not facing any issue like yours, MDIO has specific terminology to define the various devices on the bus. but Ethernet is not working in Linux kernel. 8 [ 2. MDIO has specific terminology to define the various devices on the bus. The USB-2-MDIO tool consists of an MSP430 In my case the master is communicating with multiple slaves (via MDIO / MDC) on the same bus. There are two "AXI 1G/2. The MDIO interface is implemented by two pins, an MDIO pin and a The MDIO within the PRU-ICSS in AMIC110 implements the 802. It therefore must be run with rights to Currently, the following message is printed over serial for the image runs: U-Boot 2018. 6, bus freq 1000000 (2) [ 0. ethernet: MDIO device at address 1 is missing. Contribute to tq-systems/linux-tqmaxx development by creating an account on GitHub. com> wrote: > > Calling 'mdio read ' currently leads to a data abort when no mdio > bus is found. My questions: (1) Why the MDC = 125K? On kernel log it says bus freq 1M. 758093] 8021q: adding VLAN 0 to HW filter on device 在单片机领域，通过mdio接口可以与外部设备进行通信，实现对设备的控制和数据的读写。通过本文的介绍，你可以了解到mdio接口协议的原理和使用方法，并参考源代码示例 You signed in with another tab or window. 191524] davinci_mdio 48485000. Hit any key to stop autoboot: 0 ZynqMP> mdio list No MDIO The Intel® Management Data Input/Output (MDIO) PHY management bus has two signals per MAC: MDC and MDIO. 811259] mdio_bus 2090f00. ethernet: stmmac_dvr_probe: MDIO bus (id: 1) registration failed It's perfectly fine, and the device is succesfully (and silently, as far as the console goes) probed . The problem was in our custom board circuit design. Could not get PHY for eth0: addr 12. k. suppress-preamble: [ 2. In order to Copenhagen, Denmark Sept 17-19, 2001 May 4, 2000IEEE P802. MDI0) { Device(PHY1) { Name mdio is a low-level Linux debug tool for communicating with devices attached an MDIO bus. This is mandatory for network interfaces that have PHYs Add a device tree node for the MDIO controller on the RTL9300 chips. c that allows another driver to search for a bus by name using class_find_device(). 0 EPHY: 0x0000 [Tue Jul 26 Hello i have a design where the PS MDIO_ENET0 bus is propagated through several blocks until it reaches the PL I/O Pins. 904017] mt7530-mdio mdio-bus:1f: MT7530 adapts as multi-chip module [ 2. We have a similar design where a common MDIO-0 bus of gem0 is shared with rest of the gems(gem1, gem2, gem3). We use optional cookies, as detailed in our cookie policy, to remember your settings and understand how you How to fix Zynq-7000 dual Ethernet phy on single MDIO bus in xilinx-v2019. It improves on existing tools in this space in a few important ways: MDIO buses are directly During the MDIO bus driver initialization, PHYs on this bus are probed using the _ADR object as shown below and are registered on the MDIO bus. Both phy's default to address 0x00 on the mdio bus. At 2. 5k lines) to get a [ 7. thanks for your reply! I tried it, but it is not working. mdio: davinci mdio revision 1. However, everytime the i210 starts a cycle on the MDIO bus, it stops the clock (MDC) in [ 0. I'm sure there is better way to do Hi Our custom device changed to ethernet device to Intel I210 CS and Marvell 88mQ2112 100/1000BASE-T1 Transceiver with SGMii But I210 ethernet controller cant find For each MAC node, a device property “phy-handle” is used to reference the PHY that is registered on an MDIO bus. 541269] macb ff0b0000. 930745] mt7530-mdio mdio-bus:1f: configuring for fixed/rgmii I have several devices on mdio bus - 1 phy AR8035 and 3 Dual Phys DP83849ifvs. In this case, the clock to data delay is Net: ZYNQ GEM: ff0c0000, mdio bus ff0c0000, phyaddr 7, interface rgmii-id Could not get PHY for eth0: addr 7 No ethernet found. ethernet eth0: Cadence GEM During the MDIO bus driver initialization, PHYs on this bus are probed using the _ADR object as shown below and are registered on the MDIO bus. deng@linux. As said in the reference manual, A MDIO master can use the We get the kernel Ops with enabled WED ( wifi offloading). 4 (the last version [ 6654. 1, I have a ZynqMP-based hardware configuration such that multiple PHYs are managed by a single MDIO bus, which is connected to one GEM, as in the picture below. ethernet-ffffffff: MDIO device at address 2 As per our analysis, issue in dts, Does any other change required in dts for PHY is not found on the MDIO bus issue-fix. I would suggest to talk to the phy via ioctl if the kernel driver supports it (it seems to do so via of_mdio, but I have not tried). 759391] mdio_bus 2310000. 291473] fec 30be0000. 1Q VLAN Support v1. The device driving the MDIO bus is identified as the Station Management Entity (STA). 1 @Piranha . 0 DRAM: 2 GiB EL Level: EL2 Chip ID: I basically ended up adding a helper function to mdio_bus. > > To fix The PFE2 MDIO bus is connected to a set of 4 AR8035 PHYs; The MDIO bus is able to see the AR8035 PHYs; The PHYs are connected to the SJA1105 ports via MII; PFE2 is If other PHYs are enabled in the device tree, the wonrg GEM (say GEM0) gets selected even though we clearly have configured the device tree in a fashion where GEM2 should be the > the MDIO bus hierarchy from the DTS and uses this to configure the > switch ports so they are associated with the correct PHY. ethernet: I read these document, and I set davinci_mdio, referenced k2e-net. * @mdio_bus_np: Pointer to the mii_bus. Standard properties for > > +fixed links, 'speed', 'full-duplex', 'pause', 'asym-pause', > > +'link-gpios', as defined above are Using petalinux 2019. 283508] mdio_bus 30be0000. The MDIO PHY management bus has two signals per MAC: MDC and MDIO. Refer to the W5500 Net: ZYNQ GEM: ff0c0000, mdio bus ff0c0000, phyaddr 7, interface rgmii-id Could not get PHY for eth0: addr 7 No ethernet found. ethernet eth1: Cadence MACB rev 0x0001010c at 0xf8030000 irq 28 (ee:fa: 75 Hello, We are trying to create a custom carrier for the AGX Xavier with a KSZ9897 switch chip connected to the RGMII/MDIO interface. This is a fixed PHY Identifier Register, and the PHY returns the expected └─>MDIO Bus/PHY emulation with fixed speed/link PHYs In linux kernel since version 2. * @mdio_name: The name of a mdiobus. The bottom (purple) signal is data. 744496] mt7530 mdio-bus:1f wan: configuring for phy/gmii link mode [ 6654. 1 release of U-boot During the MDIO bus driver initialization, PHYs on this bus are probed using the _ADR object as shown below and are registered on the MDIO bus. packham@alliedtelesis. 612533] Rekeying PTK for This module provides a driver for MDIO bus multiplexer that is controlled via the kernel multiplexer subsystem. New log with your changes: libphy: MACB_mii_bus: probed. The fourth Currently, the following message is printed over serial for the image runs: U-Boot 2018. Many ethernet MAC controllers also provide hardware to communicate over MDIO bus with a The check in probe_one() checks that the mdio bus number is valid whereas this checks that there are at most 4. Here a log : # ifup eth1 [ Ch1 is MDC and Ch2 is MDIO. ethernet-1: MDIO device at address 0 is missing. Description . 3 Ethernet standard and Media Independent Interface (MII). MDI0) { Device(PHY1) { Name Management Data Input/Output (MDIO) is the serial bus protocol defined in the IEEE 802. Here is log file. 975988] can: broadcast MDIO Bus: Ensure that the MDIO bus is correctly configured and that there are no conflicts with other devices on the bus. 20 (release Date: 2007-02-04) Adds the platform "fixed" MDIO Bus to cover the boards that use Using petalinux 2019. MDIO bus not found ethernet@ff0c0000 ZynqMP> Solution. This mapping is also used when dealing with ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 12, interface rgmii-id. 8, 2. [ 436. dtsi. Signed-off-by: Yajun Deng <yajun. 5 MHz, it has a zynq will have mdio bus to configure 3 PHY modules, 1 ethernet switch and 1 PCIe switch. So I tried dumping the registers on the PHY with PHY With this modification in the code, hardware designers are forced to connect reset pin of physical devices to the same GPIO used ad MDIO bus reset. Forums 5. mdio_bus e000c000. This is mandatory for network interfaces that have PHYs If other PHYs are enabled in the device tree, the wonrg GEM (say GEM0) gets selected even though we clearly have configured the device tree in a fashion where GEM2 should be the Management Data Input/Output, or MDIO, is a 2-wire serial bus that is used to manage PHYs or physical layer devices in media access controllers (MACs) in Gigabit Ethernet equipment. mdio: Linux kernel source tree. The fourth There is no need for multiple pull-ups on MDIO as that would amount to a single pull-up resistance anyway. 5MHz should only be used when all devices on the bus support. You signed out in another tab or window. MDI0) { Device(PHY1) { Name I am writing an ethernet driver that uses the cadence phy chip. I see that the mdiobus_scan() fails. And I found that if I re-boot the Uboot boot One of the devices on MDIO bus (probably the switch) is driving read data with this kind of delay. ethernet eth0: registered PHC device 0 [ 8. ethernet-ffffffff: MDIO device at address 9 is missing. MDI0) { Device(PHY1) { Name ZYNQ GEM: ff0d0000, mdio bus ff0d0000, phyaddr -1, interface sgmii Warning : ethernet@ff0d0000 using MAC address from DT , eth1 : ethernet@ff0d0000 Media Independent Interface Management (MIIM), or Management Data Input/Output (MDIO), is a serial bus protocol and is used for the IEEE 802. * Returns a reference to the mii_bus, or NULL if none found. The bus multiplexer connects one of several child MDIO busses to a parent bus. A monolithic model where the net driver itself creates, probes and uses the phy, MDIO has specific terminology to define the various devices on the bus. co. I have a board where these two lines are always printed during boot: imx-dwmac 30bf0000. 307720] sdhci Re: [PATCH net-next] net: mdio_bus: change the bus name to mdio On Thu, Dec 19, 2024 at 02:58:55PM +0800, Yajun Deng wrote: > Since all directories under the /sys/bus CONFIG_MDIO_BITBANG -mdio-bitbang. [ 3. This is mandatory for network interfaces that have PHYs [ 6. Signed-off-by: Chris Packham <chris. Scope(\_SB. mdio: MDIO device at address 0 is missing. We have found that the switch works For each MAC node, a device property “phy-handle” is used to reference the PHY that is registered on an MDIO bus. 994398] mdio_bus 4a101000. Hit any key to stop autoboot: 0 ZynqMP> mdio list No MDIO On the GEM one GEM's MDIO bus can be shared across multiple other GEMs. In the case of the W5500, the MAC and PHY are integrated in the chip. Is it I'm porting the XGS1210-12 rev. * of_mdio_find_bus - Given an mii_bus node, find the mii_bus. MDI0) { Device(PHY1) { Name Using an oscilloscope I see the clock signal of MDIO bus (MDC) is inverted as expexcted. 971752] can: raw protocol (rev 20170425) [ 7. 8 [ 0. The top (yellow) signal is clock. So not totally redundant but could probably be removed the MDIO bus hierarchy from the DTS and uses this to configure the switch ports so they are associated with the correct PHY. If all the above checks are correct and the issue I think this may be the historical bug of realtek phy. The mdio bus is controlled by AM335x SoC. MDC is the clock output, which is not free running. This is mandatory for network interfaces that have PHYs However, it can be messy, since in order to probe >>>> the MDIO bus, you probably need to take the PHY out of reset. Contribute to torvalds/linux development by creating an account on GitHub. Thanks, Muthukumar. On some router with mt7621 + rtl8211x, the realtek phy will preempt the phyad 0 of the mdio-bus, causing the port 0 of the Hi, I have three GEMs connected to DP83867 PHYs - GEM0 and 2 via GMII to RGMII IPs (addr 2 and 4) and GEM1 directly to the PHY (addr 7) With Vivado 2020. mdio: GPIO lookup for consumer reset [ 0. 5 or 3. The problem is that I can't get mdio access to Hello, I am working with imx8mp evolution kit with Android 11 OS. 892527] 8021q: 802. Every phy requires a hardware strap configuration that will set a different address Desired MDIO bus clock frequency in Hz. During heavy load on the 5GHz wifi we can get random kernel panic like below. Only the first GPIO in the Get a virtual cloud desktop with the Linux distro that you want in less than five minutes with Shells! With over 10 pre-installed distros to choose from, the worry-free maybe someone from bpi team can help me transforming the rtl8367 phy-driver to a dsa driveri have stripped needed functions from the codebase (100k => 3. 5G Ethernet subsystems" which are Hi, We have a custom zynq ultrascale board with 4 PHYs to the PS. This is a known issue in the 2020. Also, I think the module you are using is a During the MDIO bus driver initialization, PHYs on this bus are probed using the _ADR object as shown below and are registered on the MDIO bus. ethernet: Cannot register the MDIO bus imx-dwmac 30bf0000. 3 serial management interface (SMI) to interrogate and control two Ethernet PHYs simultaneously using a shared 2-wire bus. It improves on existing tools in this space in a few important ways: MDIO buses are directly MDIO is a bus that is commonly used to communicate with ethernet PHY devices. r. 961240] can: controller area network core (rev 20170425 abi 9) [ 7. For each MAC node, a device property "phy-handle" is used to reference the PHY that is registered on an MDIO bus. Typically an MDIO bus is MDIO bus not found ethernet@ff0c0000 No ethernet found. pfe0: MDIO device at address 13 is missing. -19: Broadcom UniMAC MDIO bus [Tue Jul 26 21:04:05 2022] bcmgenet fd580000. 213532] 001: mdio_bus PFEng Ethernet MDIO. This means we need to use the hardware description from the DTS to compute a mapping of Our board use two MDIO bus (ENET_MDIO1-pinE7 + ENET_MDC1-pinF9, ENET_MDIO2- pinC7 + ENET_MDC2-pinE6 ) to connect two physical ethernet. This is mandatory for network interfaces that have PHYs I know that the maximum number of devices that can be connected via MDIO bus is 32. 5G Ethernet Subsystem ip cores documentation. The pin pins used by mdio are: E7 RGMII_SMA_MDIO EQOS_SMA_MDIO E6 RGMII_SMA_MDC SMI：Serial Management Interface，也叫 MDIO BUS。 MDIO是一个以太网控制 器的传输协议，广泛用于以太网控制器和PHY之间的数据通讯。 MDIO（Management Data On Fri, Jul 12, 2019 at 1:59 PM Simon Goldschmidt <simon. So the mdio bus is reporting: [ 1. change your phy@1 reg from 1 to 0 and see if that changes. 3 standards for the Media Independent Interface, or MII. In this function, it Media Independent Interface Management (MIIM), or Management Data Input/Output (MDIO), is a serial bus protocol and is used for the IEEE 802. But how to determine the real maximum fanout of MDIO bus. Three of these PHYs are connected over GTR Lane 0,1 and 2 and in SGMII mode. *A 页3/24 interrupt — 输出 在Basic mode（基本模式）下进行配置时，只有物理地址和器件地址与先前配置的值相匹配时， 该输出才会在帧 The MDIO bus has two signals: Management Data Clock (MDC) and Managment Data Input/Ouput (MDIO). Signed-off-by: Chris Packham [Tue Jul 26 21:04:05 2022] unimac-mdio unimac-mdio. mdio: The "PHY address" you refer to is an MDIO bus address. I reproduced problem during support +config MDIO_AN8855 + tristate "Airoha AN8855 Switch MDIO bus controller" + depends on MFD_AIROHA_AN8855 + depends on OF_MDIO + help + This module provides Hy 🙂 I have a problem with the sfp located at left (eth1) I2C works : i can do the commands lines ethtool, but the network connection doesn’t work. Here is another signal capture. In our design we are using a Zynq Ultrascale+ with four DP83867s connected on a shared MDIO bus. * mdio_find_bus - Given the name of a mdiobus, find the mii_bus. ko- This module implements the MDIO bus protocol in software, for use by low level drivers that export the ability to drive the relevant pins Now, the i210 communicates to the PHY on the external MDIO bus, in MDIO mode. It is intended for debuging PHY issues, and experiementing with register settings. In Basic mode, it lets users implement their own data handling algorithms in mdio is a low-level Linux debug tool for communicating with devices attached an MDIO bus. I confirmed the PHY address anyway and the PHY address is correct. [ 8. Only the first GPIO in the The check in probe_one() checks that the mdio bus number is valid whereas this checks that there are at most 4. MDI0) { Device(PHY1) { Name MDIO Bus Scope Traces. Figure 3 shows a scope trace of an MDIO read cycle performed by the FPGA at register address 0x3 of the DP83867. 0 DRAM: 2 GiB EL Level: EL2 Chip ID: The kernel switch device driver uses the mdio bus independently. 3). MDIO signals • MDC (Management Data Clock) sourced continuously from STA (station management entity) • MDIO (Management Data Input/Output) bi-directional multi -drop bus Management Data Input/Output, or MDIO, is a standard-driven, dedicated-bus approach that's specified in IEEE RFC802. 3 standard for Ethernet for the Media Independent Interface (MII). 533394] mdio_bus ff0b0000. MII connects Media Access 当前mac contorller是使用Cadence的IP核，phy使用的是icplus的ip1001C,在硬件相同的前提下，内核版本不同，在使用3. Change the bus name to mdio. pfe0: MDIO device at address Linux kernel source tree. S. imx-dwmac 30bf0000. I plan to use these level translators to match the voltage of each the slaves (1. As an experiment I am trying to use the official in-tree MT7530 DSA module. MDI0) { Device(PHY1) { Name mdio_bus 8000f00. Did I miss anything in the dts file? [ 3. Here is an example of the MDIO interface used for communication between the Station Management device (STA) and MDIO Manageable devices (MMD). I could not find anything regarding that on the AXI 1G/5. You would look at MAC or PHY requirements for pull-up resistance The MDIO Interface component supports the Management Data Input/Output, which is a serial MDIO bus. The target devices that are being managed by the MDC are referred to as We use some essential cookies to make our website work. MDI0) { Device(PHY1) { Name With this modification in the code, hardware designers are forced to connect reset pin of physical devices to the same GPIO used ad MDIO bus reset. 3 Ethernet standard During the MDIO bus driver initialization, PHYs on this bus are probed using the _ADR object as shown below and are registered on the MDIO bus. root@OpenWrt:/# dmesg | grep For each MAC node, a device property “phy-handle” is used to reference the PHY that is registered on an MDIO bus. The PHYs are TI's DP83867. The MDIOS peripheral in our MCU serves as a slave interface to a MDIO bus. ethernet eth1: Cadence MACB rev 0x0001010c at 0xf8030000 irq 28 (ee:fa: 75 The phy driver makes use of phycontrol libraries and the MDIO read/writes are working good, except that from time to time I encounter strange network link loss/recover on the serial For each MAC node, a device property "phy-handle" is used to reference the PHY that is registered on an MDIO bus. MDIO (Management Data Input/Output) Introduction to MDIO: Management Data Input/Output (MDIO), or Media Independent Interface Management (MIIM) is a serial bus protocol defined Here is an example of the MDIO interface used for communication between the Station Management device (STA) and MDIO Manageable devices (MMD). 260547] random: crng init done [ 1. [ 784. No ethernet found. Typically an MDIO bus is This is a utility to make it easy to interact with the PHY(s) attached to the MDIO bus from usermode under linux. I mean I have a PCB (6U Hi Igor, thanks for your help. 975223] libphy: Fixed MDIO Bus: probed [ 0. This mapping > is also used when dealing with OK libphy: MACB_mii_bus: probed [ 3. 3. B1, and the plain gigabit and SFP+ ports seem to work as expected. I'm working on a custom Zynq-7000 card is currently using Xilinx Linux v2017. defined 2. 6. mdio: davinci mdio Now, the i210 communicates to the PHY on the external MDIO bus, in MDIO mode. >>>> >> >> But the DT binding documentation Hello @shabbirk ,. 01 (Feb 13 2020 - 21:18:13 \+0000) Xilinx ZynqMP ZCU102 rev1. Please note that in this case there could be some kind of MDIO support must be enabled in the IP core at compile time. However, everytime the i210 starts a cycle on the MDIO bus, it stops the clock (MDC) in Part Number: AM6411 Other Parts Discussed in Thread: TPS65220, SK-AM64B Hello i would like to better understand what it is mandatory for having Boot over ethernet > petalinux-boot --qemu --u-boot ZYNQ GEM: e000b000, mdio bus e000b000, phyaddr 0, interface rgmii-id eth0: ethernet@e000b000 also i'm try to figure what is change linux tree for TQ Systems ARM based SOM. I **BEST SOLUTION** Hey John, you are good, it works! The additional statements in the phy section helped and the board boots now on an Gigabit Switch (of course using only a 100 During the MDIO bus driver initialization, PHYs on this bus are probed using the _ADR object as shown below and are registered on the MDIO bus. 729554] mt7530 mdio-bus:1f wan: Link is Down [ 6654. However, my driver is failing to scan the cadence phy chip. So not totally redundant but could probably be removed I read these document, and I set davinci_mdio, referenced k2e-net. The MDIO bus¶ Most network devices are connected to a PHY by means of a management bus. 5G PHYs are RTL8221B though (unlike the A1 which had 8226 Hello @Msams. [ 6. 213800] 001: mdio_bus PFEng Ethernet MDIO. 319402] davinci_mdio 4a101000. The 2. The USB-2-MDIO software tool allows users of Texas Instruments' Ethernet PHYs to access MDIO status and control registers. [ 0. The It appears most ethernet drivers follow one of two main strategies for mdio bus/phy management. 2 PHY - 88E1512 probably wont need any configuration change - will work exactly as on EVB. nz>---Notes: Changes in v4: Since all directories under the /sys/bus are bus, we don't need to add a bus suffix to mdio. ethernet: GENET 5. 1 PHY Hi, We have a custom zynq ultrascale board with 4 PHYs to the PS. I have checked and verified strapping, MDIO addressing, MDIO timing and the actual MDIO communication to and from the PHYs on The MDIO bus doesn't appear the the device tree but I've noticed some folks include mdio as a child to GEM and other threads say the MDIO bus is sometimes provided as a separate node. 256118] libphy: Fixed MDIO Bus: probed [ 1. 792530] mdio_bus f8030000. I want to work with Both On board Ethernet (eth0 and eth1) By default eth0 which is fec controller is working I notice one of my AP suddenly downgraded connection from 1Gbps/Full to 100Mbps/Full, I saw some strange kernel logs as follows, [1152623. 3ae MDC/MDIO Slide – V1. Different devices use different busses (though some share common interfaces). 799928 ] macb f8030000. You switched accounts on another tab > > +Child nodes represent PHYs on this mdio bus. dev> Hi, We are trying to bring up dp83867IR on a ZYNQ MPSOC platform, But i am getting PHY is not detected message. 01 IEEE 802. 994386] mdio_bus 4a101000. 14内核版本时，mac 驱动使用的是emacps driver，此时能正确读取phy * of_mdio_find_bus - Given an mii_bus node, find the mii_bus. The MIIM/MDIO During the MDIO bus driver initialization, PHYs on this bus are probed using the _ADR object as shown below and are registered on the MDIO bus. The MII connects media access control (MAC) devices with Ethernet physical layer (PHY) circuit The MDIO PHY management bus has two signals per MAC: MDC and MDIO. the given clock speed. Kindly check and update. 967375] NET: Registered protocol family 29 [ 7. Management Data Input/Output (MDIO), also known as Serial Management Interface (SMI) or Media Independent Interface Management (MIIM), is a serial bus defined for the Ethernet family of IEEE 802. 1 and standalone application This series adds a driver for the MDIO controller on the RTL9300 family of devices. 3ah Task Force Slide 1 IEEE P802. 5 MHz, it has a 400 ns minimum period. mdio: using [ 8. 299761] imx-spdif sound-spdif: ASoC: failed to init link S/PDIF PCM: -517 [ 8. Reload to refresh your session. switch port number to actually communicate over the MDIO bus this needs to be supplied via the "realtek,port" property. 3ae MDC/MDIO Ed Turner – Clause 45 editor MDIO 接口 Document Number: 001-89719 Rev. 1 and newer.